The present invention relates to a clock recovery system, and more particularly to an open loop phase locked clock recovery oscillator circuit for recovering a clock signal from a high speed small amplitude data stream.
High speed, low power clock recovery circuits find wide applications in high performance communications systems. For example, clock recovery circuits have been used at the front-end of fiber-optic receivers. Clock recovery circuits allow recovery of a clock signal from a potentially small amplitude data stream so as to regenerate the data stream at its original frequency. Phase detectors are typically used for clock recovery from a non-return-to-zero (NRZ) data stream.
However, when the speed of the data stream is at the limits of the technology, it is impossible to use conventional phase detectors that rely on a phase difference measurement. At extremely high speeds, recovery circuits can only sample the data at the data transition moment to determine a late or early digital phase sample. This is especially true when the clock recovery is performed in CMOS (complementary metal-oxide-semiconductor) for data rates of 2 Giga-bits per second for example. Additionally, conventional analog techniques require a low pass filter to store a control voltage, which takes up large amounts of area in integrated form and is susceptible to noise coupling. Also conventional analog techniques to perform clock recovery can only achieve recovery bandwidths of around 1/50th or less of the data rate due to stability issues as a result of the loop delay, creating destabilizing phase shift.
Continuous time processing clock recovery circuits for example, LC-tuned filters or quadricorrelators have been explored and hold promise of lower power since the extra high speed clocks and circuitry used solely for sampling the data during potential data transitions are avoided. However, it is extremely difficult to accomplish these methods in mainstream digital CMOS.
One form of nonlinear continuous time processing clock recovery circuit has been proposed by B. Razavi in "A2.5-Gb/s 15 m-mW Clock Recovery Circuit," IEEE J. Solid-State Circuits, vol. 31, pp 472-480, April 1996. This article describes the design of a high-speed clock recovery circuit fabricated in a 20 GHz 1-.mu.m BiCMOS technology. However, the design uses a bipolar system, which is not suitable for CMOS technology. Also, the control loop can present stability problems.